A phase locked loop (PLL) or a DLL both require a phase detector as a fundamental functional block. The PLL utilizes the phase detector with a voltage controlled oscillator (VCO) to generate high frequencies that are a multiple of a reference clock that is generated to have a stable frequency. The output of the VCO is frequency divided to generate a divided clock. The divided clock is phase compared with the reference clock thereby generating an error signal. The error signal is used to control the VCO. Increasing the VCO frequency makes transitions occur earlier and decreasing the VCO frequency makes transitions occur later relative to the reference frequency. Using a phase comparator and the VCO in this manner allows the divided frequency to phase lock with the reference frequency when in a closed loop feedback system. Depending on the type of phase detector, a PLL may generate a divided frequency that is phase and frequency locked to the reference and a VCO clock that is a multiple of the reference frequency.
In a DLL, two signals that have the same frequency but are phase shifted may be phase aligned by adding delay to one of the signals. If the delay line used to add delay is voltage controlled, then a phase detector that measures the phase shift may be used to produce an error signal that adds delay to one signal until the error signal is minimized. For example, in clock distribution between systems or chips it may be desirable to have the clock used throughout the systems to be synchronous, each clock edge occur at the same time. A DLL may be used to align the clock signals in two separated systems so that the clocks in both systems are synchronous even though they may be separated by a significant delay time relative to their clock period. The higher the clock frequency the more this is a problem. If clocks cannot be aligned, then the clock frequency in a synchronous system may be high frequency limited.
Most phase detectors produce an error signal proportional to the actual phase angle shift between the two signals. In logic systems, the signals are binary and the phase error can only be determined each clock cycle. If the phase error is leading, then the voltage controlling the delay line needs to slew in one direction (e.g., increase) and if the phase error is lagging, then the voltage needs to slew in the other direction (e.g., decrease). A charge pump is a circuit where a capacitor is charged and discharged with current sources to produce an increasing or decreasing voltage with a DC value proportional to the time difference between charge and discharge cycles. Typically, pulse generators are used to produce a pulse on the clock signal edges wherein the pulses are used to set and reset a latch whose normal and inverting outputs are used to control the charge and discharge of the capacitor in the charge pump. However, if the clocks are high frequency, then the pulses that must be generated each clock cycle must be correspondingly very short. The circuitry to generate the pulses adds power and the short pulses may introduce jitter to the delayed clock.
There is, therefore, a need for a phase detector directed to the requirements of a DLL used to align very high frequency clocks without producing pulses on each clock edge thus reducing power and decreasing clock edge jitter.